On Monday, Intel and Synopsys announced a strategic partnership that includes development of a portfolio of intellectual property (IP) for the Intel 3 and 18A process nodes. This is a significant announcement for customers and prospect considering Intel Foundry Services (IFS) as a potential semiconductor foundry for advanced integrated circuits (ICs). The agreement is not exclusive, which is a good thing for IFS, because semiconductor foundry customers often need IP from multiple vendors to complete their IC designs.
Having Synopsys as a strategic IP and Electronic Design Automation (EDA) partner bolsters IFS’s credibility as a major foundry player. It’s not possible for any semiconductor foundry to be considered a major player without similarly engaging top IP and EDA vendors, because foundry customers want and demand choice. EDA partners in the IFS Accelerator Ecosystem Alliance already include Cadence and Siemens, as well as Synopsys. IP partners include microprocessor IP heavyweights such as Andes, Arm, and SiFive in addition to IP vendors with broad IP libraries such as Cadence and Synopsys.
The agreement is also a good deal for Synopsys, because it ensures ready access to Synopsys IP by another bleeding-edge semiconductor vendor. With Intel’s declared intent to regain semiconductor process leadership by 2025, IFS will surely be a very important foundry partner for Synopsys.
According to Rahul Goyal, Vice President of Product & Design Ecosystem Enablement at IFS, there will be no relocation or transfer of Intel IP engineers to Synopsys due to this agreement. Synopsys is largely porting elements of its existing IP library to the Intel 3 and 18A process nodes. The agreement is not limited to these process nodes. Both Intel and Synopsys characterize this agreement as a multi-year, multi-generational agreement. According to John Koeter, SVP of IP Product Management and Strategy at Synopsys, the agreement includes a framework for extending the strategic partnership to future process nodes beyond Intel 18A.
The Intel 3 process is established, and Intel announced during an earnings call early this year that it already has an IFS customer that’s a major “cloud, edge, and datacenter solutions provider” for this process node. The Intel 18A process node is still under development and is scheduled to be “manufacturing ready” sometime in 2024. In July, IFS announced that Boeing and Northrop Grumman are customers for the Intel 18A process node as part of phase two of the U.S. Department of Defense (DoD)’s Rapid Assured Microelectronics Prototypes – Commercial (RAMP-C) development program. The DoD developed the RAMP-C program to help companies in the Defense Industrial Base (DIB) to fabricate leading-edge custom ICs that will be required for future, advanced defense systems.
This announcement is yet another milestone along the road to success that Pat Gelsinger has mapped out for Intel to regain the company’s leadership position in chipmaking. Recently, Gelsinger combined IFS with Intel semiconductor manufacturing and packaging operations and TD, the company’s process technology development group. (See “Pat Gelsinger’s Plan To Fix Intel.”)
Gelsinger then gave this organization its own profit and loss (P&L) statement, reporting directly to him. This is a master strategic move to require Intel manufacturing to prove itself in the real world, with real competitors – other foundries in this case. The P&L makes visible every cost – chip revisions, expedited orders, special process tweaks, and so on – that were once absorbed as corporate overhead. It also makes the Intel business units more financially responsible for their behavior than ever before, all of which should be good for Intel, however the proof is in the execution. Meanwhile, Intel continues to spend billions of dollars on new fabs to prepare for the day when the company has gotten back its process mojo. (See “Bad Times For Intel. Will They Last Forever?”)
We’ll need to wait a while to see how effective Gelsinger’s strategy will be in restoring Intel to its former self.
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